1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a high voltage MOS transistor.
2. Description of Related Art
An example of a conventional high voltage MOS transistor is shown in FIGS. 6A and 6B. FIG. 6A is a plan view of the conventional high voltage MOS transistor. FIG. 6B is a cross-sectional diagram taken along the line VIB-VIB of FIG. 6A. Incidentally, FIG. 6A shows a state when a gate electrode is removed and a gate electrode area is indicated by a chain line.
In FIGS. 6A and 6B, a conventional high voltage MOS transistor 1 includes a P−− type silicon substrate 2, a P− type punch through prevention region 3, an N− type drain offset region 4, an N+ type source region 5, an N+ type drain region 6, a gate insulating film 7, a gate electrode 9, a P+ type back gate region 10 and a channel region 11.
The gate electrode 9 is formed over the P−− type silicon substrate 2 with the gate insulating film 7 interposed therebetween.
The N+ type source region 5 is formed to be adjacent to one end of the gate electrode 9 in plan view.
The N− type drain offset region 4 for obtaining high voltage characteristics is formed to face the source region 5 with the channel region 11 interposed therebetween.
The N+ type drain region 6 is formed away from another end of the gate electrode 9 to be included in the drain offset region 4.
The P− type punch through prevention region 3 is formed to surround the drain offset region 4 in plan view.
Moreover, the P+ type back gate region 10 for isolation is formed in the peripheral portion of the active region.
The reason why the drain offset region 4 and the punch through prevention area 3 are provided to be in contact with each other is to prevent from an extension of diffusion in the horizontal direction so as to reduce the size in plan view (See for example Japanese Unexamined Patent Application Publication No. 2005-167262).
In the conventional high voltage MOS transistor 1 including the N type drain offset region 4 and the P type punch through prevention region 3 provided to be in contact with each other over the surface of the P type silicon substrate 2, when applying a high voltage to the drain region 6, as shown in FIG. 7A, a depletion layer (indicated by the broken line) expands in a PN junction surface between the drain offset region 4 and the silicon substrate 2 and in another PN junction surface between the drain offset region 4 and the punch through prevention region 3, thereby reducing an electric field.
Here, as the P type impurity concentration of the silicon substrate 2 is lower than the P type impurity concentration of the punch through prevention region 3, the depletion layer width “a” generated in the PN junction surface between the silicon substrate 2 and the drain offset region 4 is wider than the depletion layer width “b” generated in the PN junction surface between the punch through prevention region 3 and the drain offset region 4.
Accordingly, a so called avalanche breakdown, which is generated when exceeding a critical electric field, is generated in the PN junction surface between the punch through prevention region 3 and the drain offset region 4.
Furthermore, as shown in FIG. 7B, in the PN junction surface between the punch through prevention region 3 and the drain offset region 4, especially immediately below the gate electrode 9, the avalanche breakdown could be generated, and when an avalanche current Ia flows, a parasitic bipolar transistor (NPN) Tr operates and a breakdown voltage between drain and source could decline.